Ferroelectric based capacitors are in increasing demand as integrated circuit elements. Capacitors having platinum lanthanum titanium zirconate (PLZT) dielectrics offer large dielectric constants which in turn make the construction of small capacitors with relatively large capacitances possible. A ferroelectric capacitor consists of a PLZT layer sandwiched between two planar electrodes. Capacitors utilizing platinum electrodes are particularly advantageous, since such capacitors exhibit reduced aging effects compared to capacitors utilizing other electrode materials.
The bottom electrode of a PLZT capacitor is typically deposited on the semiconductor surface or a SiO.sub.2 layer thereon. To "stick" the platinum layer to the silicon, a titanium layer is deposited on the silicon surface prior to depositing the platinum layer. During the subsequent deposition of the PLZT material and the annealing thereof, the titanium tends to diffuse into the platinum. If the platinum layer is too thin, the titanium will reach the PLZT surface and form an oxide thereon which interferes with the operation of the capacitor; hence, relatively thick (&gt;1000 .ANG.) platinum layers must be employed.
It is difficult to pattern such thick electrode structures, particularly in those cases in which small platinum structures must be generated. In principle, the platinum can be patterned using photoresist methods, ion milling, or etching with hot aqua regia. If small features are to be generated, hot aqua regia etching is unsatisfactory because it results in undercutting of the platinum structure; hence, the minimum feature size is limited by thickness of the platinum layer. Ion milling produces satisfactory structures, but requires expensive equipment, and is difficult to control. Hence, the method of choice is a lift-off process using photoresist.
Unfortunately, prior art photoresist processes are found to be unsatisfactory when applied to platinum electrodes for PLZT structures such as capacitors. The photoresist process leaves material on the surface of the silicon substrate which reduces the strength of the bond between the SiO.sub.2 and the titanium-platinum layer. In subsequent PLZT deposition and annealing steps, the bond is stressed by the expansion and contraction of the PLZT layer which is in contact with the platinum. The stress is sufficient to cause the platinum layer to separate from the SiO.sub.2 substrate.
Broadly, it is the object of the present invention to provide an improved lift-off process for patterning platinum structures on integrated circuits.
It is a further object of the present invention to provide a lift-off process which produces platinum structures that can withstand the physical stress of PLZT deposition and annealing without detaching from the underlying substrate.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.